1. Field of the Invention
The present invention relates generally to wafer inspection, and more specifically to a method and system for identifying systematic defects in wafer inspection.
2. Description of Related Arts
Producing semiconductors requires a very cost-intensive and sophisticated manufacturing environment. With the size of the structures built on a semiconductor device decreasing, the production costs are increasing at the same pace. Semiconductor production in a modern fab requires several hundreds of machines, with prices reaching several ten-millions or even hundred-millions of US dollars per machine.
The process of semiconductor device manufacturing often requires hundreds of sequential steps, each one of which could lead to yield loss. Consequently, maintaining product quality in a semiconductor manufacturing facility often requires the strict control of hundreds or even thousands of process variables. The issues of high yield, high quality and low cycle time are being addressed in part by the ongoing development of several critical capabilities, i.e. process monitoring, process/equipment modeling, process optimization, process control, equipment and process diagnosis and parametric yield modeling.
During the manufacturing of a semiconductor device, inspection is typically performed by illuminating the manufactured semiconductor wafer using optical sources or electron beams and then analyzing the signals returned from the semiconductor wafer. As the design rule shrinks, the circuit patterns on the semiconductor wafer become very small and dense. Defect signals that can be detected from the inspection are extremely weak and often in the order of the normal variation caused by the manufacturing process. As a result, critical defects of interest can be missed or embedded in thousands or millions of nuisances in the candidate defect list of an inspection result.
FIG. 1 is an exemplary wafer map showing the candidate defect distribution on a wafer of a typical candidate defect list from wafer inspection. As can be seen, the candidate defects generated by the inspection span across the whole wafer and the majority of them are nuisances. Because of the small geometries of the circuit pattern, the image of a candidate defect acquired from the inspection often either shows only a single pixel in the defective area or is not resolvable at all. Semiconductor manufacturers face the challenge of identifying whether the candidates are real killer defects or just nuisances. What makes the inspection further more difficult is that many systematic critical defects are undetectable because their signatures appear no difference from the nuisances in the inspection.
Many signal and image processing techniques have been applied in wafer inspection, trying to eliminate the nuisances and identify real defects that may make the semiconductor device mal-function. In general, inspection results from a handful of wafers are used to optimize the recipes for inspecting future wafers with desired sensitivity and acceptable number of total candidate defects, or train the templates for classifying real defects from nuisances.
As the advanced semiconductor technology pushes the physics limits to shrink the size of the device, conventional methodology of simply analyzing returned signals by illuminating wafer one by one using optical sources or electron beams is no longer sufficient. Critical systematic defects may be barely detectable even though they exist in many locations in a wafer. Eliminating the systematic defects is a huge challenge in ramping up the manufacturing process for volume production. In the volume production, newly occurring systematic defects also have to be identified as early as possible to avoid losing all the manufactured wafers, the ones in the manufacturing pipeline as well as those already being completed.